This section is intended to provide a background or context to this invention. The description herein may include concepts that could be pursued, but are not necessarily ones that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, what is described in this section is not prior art to the description and claims in this application and is not admitted to be prior art by inclusion in this section.
Memory components continue to proceed towards smaller and smaller sizes (e.g., current devices use 56 nm technologies, while future device may use 43 nm and 32 nm). For at least this reason, newer memory devices may become aged and corrupted faster than in prior generations.
Many memory components (e.g., NAND memory devices) are sensitive to temperature. In high temperature environments memory units may quickly become permanently corrupted. Thus, high temperatures can decrease the amount of allowed memory write/erase (W/E) cycles over a lifetime of the memory component.
Aging of the memory may depend on the particulars of the memory device, ambient temperatures, usage conditions and actual usage of the memory device.
Additionally, certain memory systems (e.g., flash memory) also experience “read-disturb” type failures. These failures occur when data in a first area which is adjacent to a second area is unintentionally altered due to activity in the second area.
Therefore, the reliability of memory components (e.g., max program erase (PE) cycle count, data retention, read/program disturbs, etc.) will become an even more important issue.
What is needed is a means to predict data corruption in a memory device that does not necessarily rely on a pre-determined fixed threshold.